Manufacturers of semiconductor devices routinely test their products at the wafer level and the packaged-device level using sophisticated test systems commonly referred to as automatic test equipment. The equipment generally drives waveforms to and detects outputs from one or more integrated circuits of a wafer under test. Detected outputs are compared against known good values or ranges to determine whether the integrated circuit is functioning properly. It is beneficial to identify defective integrated circuits on a given wafer before any further effort is made in packaging defective integrated circuits.
A focus of semiconductor manufacturers is improving test throughput to process the highest possible volume of integrated circuits in a most economical manner using automated test systems. Efficient testing of semiconductor devices generally requires an apparatus to move and quickly connect the integrated circuit to the tester. A machine specially adapted to move wafers is referred to as a prober, or more generally as handling apparatus.
One approach to improving throughput at wafer-level test involves testing multiple integrated circuits of a single wafer at substantially the same time. Wafer-interface probes have been developed together with test systems to probe and test multiple integrated circuits during a single touch down of the probe onto the wafer. Despite this approach, multiple touchdowns are still typically required to test all of the integrated circuits of a single wafer. Inefficiencies are introduced when simultaneously probing multiple integrated circuits due at least in part to the circular shape of the wafer substrate; the rectangular arrangement, or lattice, of integrated circuits provided thereon; and the square or rectangular shape of the probing head. Namely, some of the probes do not land on integrated circuits during touch downs performed along the edge portions of the wafer. Consequently, some of the channels available on the test system are left unused. Unused test resources represents an inefficiency resulting in more touchdowns being necessary to test all of the integrated circuits of a single wafer.
Alternatively or in addition, some of the probes may touchdown on the same integrated circuit more than once as a wafer-interface probe is positioned and repositioned to test all of the integrated circuits of a single wafer. Again this results in an inefficient use of test resources.